Hierarchy	Input	Constant Input	Unused Input	Floating Input	Output	Constant Output	Unused Output	Floating Output	Bidir	Constant Bidir	Unused Bidir	Input only Bidir	Output only Bidir
timer|counter	3	1	0	1	32	1	1	1	0	0	0	0	0
timer	2	1	0	1	8	1	1	1	0	0	0	0	0
sdata_ins	13	1	10	1	7	1	1	1	0	0	0	0	0
i2c_slave_modul|I2C_WDT_I	4	1	0	1	1	1	1	1	0	0	0	0	0
i2c_slave_modul|i2c_slave	19	1	0	1	19	1	1	1	0	0	0	0	0
i2c_slave_modul|i2c_sda_de	2	0	0	0	1	0	0	0	0	0	0	0	0
i2c_slave_modul|i2c_sck_de	2	0	0	0	1	0	0	0	0	0	0	0	0
i2c_slave_modul	19	7	0	7	19	7	7	7	0	0	0	0	0
UUT1|reset_timer3_a|timer|counter	3	1	0	1	32	1	1	1	0	0	0	0	0
UUT1|reset_timer3_a|timer	2	0	0	0	6	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u12|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u12	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u11|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u11	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u10|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u10	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u9|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u9	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u6|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u8|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u8	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u7|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u7	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u5|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u5	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u4|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u4	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u3|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u3	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u2|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u2	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u1|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a|u1	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer3_a	2	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|timer|counter	3	1	0	1	32	1	1	1	0	0	0	0	0
UUT1|reset_timer2_a|timer	2	0	0	0	6	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u12|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u12	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u11|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u11	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u10|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u10	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u9|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u9	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u6|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u8|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u8	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u7|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u7	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u5|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u5	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u4|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u4	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u3|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u3	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u2|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u2	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u1|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a|u1	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer2_a	2	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|timer|counter	3	1	0	1	32	1	1	1	0	0	0	0	0
UUT1|reset_timer1_a|timer	2	0	0	0	6	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u12|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u12	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u11|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u11	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u10|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u10	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u9|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u9	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u6|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u8|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u8	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u7|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u7	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u5|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u5	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u4|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u4	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u3|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u3	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u2|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u2	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u1|U6	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a|u1	3	0	0	0	1	0	0	0	0	0	0	0	0
UUT1|reset_timer1_a	2	0	0	0	2	0	0	0	0	0	0	0	0
UUT1	8	10	0	10	10	10	10	10	0	0	0	0	0
inst_pch_syspwrok	34	32	0	32	1	32	32	32	0	0	0	0	0
inst7_pchpwrok_dly	34	32	0	32	1	32	32	32	0	0	0	0	0
BCM5720_PERST_L_delay	34	32	0	32	1	32	32	32	0	0	0	0	0
inst_pwrgd_pch_p1V5_dly	34	32	0	32	1	32	32	32	0	0	0	0	0
inst5_vccin_dly	34	32	0	32	1	32	32	32	0	0	0	0	0
inst4_slpS4_dly	34	32	0	32	1	32	32	32	0	0	0	0	0
inst4_cpu_rsmrst_dly	34	32	0	32	1	32	32	32	0	0	0	0	0
inst3_sc_pwrgd_dly	34	32	0	32	1	32	32	32	0	0	0	0	0
inst2_apwrok_dly	34	32	0	32	1	32	32	32	0	0	0	0	0
inst_p3v3_gd	34	32	0	32	1	32	32	32	0	0	0	0	0
inst1_pwrgd_stby	34	32	0	32	1	32	32	32	0	0	0	0	0
inst_pwrgd_stby2	34	32	0	32	1	32	32	32	0	0	0	0	0
inst_pwrgd_stby	34	32	0	32	1	32	32	32	0	0	0	0	0